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Giorgi Gogitidze

Engineering case study

USB Mixed-Signal STM32 Data-Acquisition Board

Schematic-ready two-channel Rev-A architecture with protected analog inputs, SPI conversion, framed USB transport, and a Python host workflow.

  • Schematic-ready design
  • Analytical calculation
  • Automated test

Problem statement

Design a buildable first-revision acquisition board that exposes the real interfaces among analog conditioning, conversion, firmware buffering, USB transport, layout, and verification without overstating unbuilt hardware.

A mixed-signal design package connecting electrical requirements and PCB constraints to portable embedded logic, host-side capture, and an explicit hardware bring-up plan.

20 kS/s/ch

Sampling target

Two channels; not yet measured on target hardware

12 bit

Nominal conversion

0.806 mV ideal LSB at a 3.3 V reference

10.61 kHz

Input RC pole

First-order anti-alias aid above the 5 kHz useful band

250 kHz

PWM carrier

Filtered for slow analog stimulus, not precision generation

Project scope

  • Two protected 0-3.0 V inputs and a 20 kS/s-per-channel target
  • STM32G0B1, MCP3202 12-bit SPI ADC, TLV9062 buffers, USB-C power/data, and SWD
  • 250 kHz PWM with a two-pole RC output for slow stimulus and loopback testing
  • Schematic-ready connections and layout plan; no KiCad PCB, fabrication, or bench measurements

System or processing architecture

USB-C supplies 5 V and CDC transport. A protected LDO creates digital 3.3 V and a ferrite-fed analog zone over one continuous ground plane. Buffered RC-filtered inputs feed the external ADC; timer-driven firmware fills ping-pong buffers and emits sequence- and CRC-protected frames.

My engineering contributions

  • Converted acquisition goals into measurable electrical, timing, interface, and bring-up requirements.
  • Selected the MCU, ADC, op amp, regulator, protection approach, and assembly-friendly packages through a documented trade study.
  • Defined schematic-ready connections, pin assignments, floorplan, return-path rules, BOM, and Rev-A risk controls.
  • Implemented portable buffering, framing, CRC, PWM math, and a Python parser/simulated capture workflow.

Important design decisions

  • Selected a 12-bit SOIC ADC over a higher-resolution delta-sigma device to reduce Rev-A clocking, front-end, and assembly risk.
  • Used one continuous ground plane with placement-based analog/digital partitioning to preserve return-current paths.
  • Kept USB transfer outside the sampling callback and added sequence, status, and CRC fields so transport failures are observable.

Engineering methods

  • RC cutoff, quantization, power, and ideal PWM-ripple calculations
  • Mixed-signal placement and return-path planning
  • Ping-pong acquisition buffering and CRC-16-CCITT framing
  • Native C unit tests and host parser simulation
  • Staged power, USB, ADC, output, loopback, and sustained-stream bring-up plan

Selected evidence

Readable results, with context

STM32 mixed-signal DAQ architecture from USB-C through the MCU, ADC inputs, and PWM output
Figure 1Rev-A functional architecture linking USB power/data, conversion, acquisition control, and filtered output.
DAQ power tree separating protected USB input, digital 3.3 V, and ferrite-fed analog 3.3 V
Figure 2Power and placement domains share one continuous ground plane; the ferrite separates supply noise, not ground nets.
Simulated two-channel voltage capture produced by the Python DAQ host utility
Figure 3Host-side simulated capture verifies parsing, engineering-unit conversion, CSV export, and plotting—not analog hardware performance.

Verification and testing

  • The calculation script produces filter, quantization, thermal, data-rate, and supply-current results.
  • Portable native tests exercise CRC, frame structure, buffer transitions, sequence behavior, and PWM conversion.
  • Python tests exercise frame parsing and simulated host capture with CSV and plotted output.
  • Hardware acceptance is deliberately deferred to target compilation, KiCad ERC/DRC, fabrication review, and bench bring-up.

Honest limitations

  • No schematic capture, PCB layout, ERC, DRC, Gerber review, assembled board, or electrical measurement has occurred.
  • Native tests do not prove STM32 HAL integration, SPI timing, USB enumeration, or interrupt latency.
  • The 3.3 V rail doubles as the ADC reference and the one-pole input filter provides limited Nyquist rejection.
  • The board is non-isolated, uncalibrated, and not a safety- or measurement-certified instrument.

Tools and technologies

  • STM32G0
  • MCP3202
  • TLV9062
  • USB CDC
  • SPI
  • C11
  • Python
  • CMake
  • Mixed-signal PCB design

Skills demonstrated

  • Mixed-signal design
  • Embedded C
  • USB and SPI
  • PCB layout planning
  • Data acquisition
  • Design verification

Downloadable proof of work

Review the evidence directly

Design reportPDF · architecture, decisions, and verification boundaryDownload →BOM workbookXLSX · Rev-A planning BOMDownload →Source and evidence bundleZIP · hardware package, source, tests, and resultsDownload →

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